PO74HSTL314A
3.3V 2:4 Differential Clock/Data Fanout Buffer
500MHz HSTL Potato Chip
08/03/06
Pin Definitions
Pin
1, 10,11,20,3
2
4
5
6
7
8
9
18, 16,14,12
19, 17,15,13
VCC
NC
CLK_SEL
CLKA
CLKA#
CLKB
CLKB#
VEE
Q[0:3]#
Q[0:3]
I,PD
I,PD
I,PU
I,PD
I,PU
GND
O
O
LVCMOS
Name
I/O
VCC
Type
Power
No connect
Input clock select with pull down resistor
LVDS, PECL, HSTL
Default differential clock input
LVDS, PECL, HSTL
Input clock select with pull up resistor
LVDS, PECL, HSTL
Input clock select with pull down resistor
LVDS, PECL, HSTL
Input clock select with pull up resistor
Description
Power supply, positive connection
Power
HSTL
HSTL
Power Ground
Complement output
Ture output
Function Table
Control
CLK_SEL
0
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with LVDS, ECL, PECL, HSTL or
TTL compatible signals with respective power configurations
CLKB, CLKB# input pair is active
CLKB can be driven with LVDS, ECL, PECL, HSTL or
TTL compatible signals with respective power configurations
1
Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
88
88
Maximum
Units
pF
K
Ω
K
Ω
2
Copyright
© Potato Semiconductor Corporation
POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
