PO74HSTL85353A
www.potatosemi.com
LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer
300MHz HSTL Potato Chip
Pin Definitions
Pin
10,13,18
5, 8, 9
3
4
6, 7
2
1
19, 16,14,11
20, 17,15,12
VCC
NC
CLK_SEL
CLK0
XTAL_IN XTAL_OUT
Name
I/O
VCC
I,PD
I,PD
I
I,PU
GND
O
O
Type
Power
LVCMOS
No connect
Description
Power supply, positive connection
Input clock select with pull down resistor
LVCMOS/ LVTTL
LVCOMS / LVTTL clock input
LVCMOS/ LVTTL
crystal oscillator interface
LVCMOS/ LVTTL
Clock enabled
CLK_EN
VEE
Q[0:3]#
Q[0:3]
Power
HSTL
HSTL
Power Ground
Complement output
Ture output
Control Input Function Table
CLK_EN
0
0
1
1
CLK_SEL
0
0
1
Inputs
Selected Source
CLK
CLK
Q0:Q3
Disabled; LOW
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
XTAL_IN, XTAL_OUT
XTAL_IN, XTAL_OUT
Disabled; LOW
Enabled
1
Input/ Output Function Table
Inputs
CLK
0
1
Q0:Q3
LOW
HIGH
Outputs
nQ0:nQ3
HIGH
LOW
Pin Characteristics
R
PULLUP
C
IN
Symbol
Input Capacitance
Parameter
Test Conditions
Minimum
Typical
88
88
4
Maximum
Units
K
K
pF
Input Pullup Resistor
R
PULLDOWN
Input Pulldown Resistor
Potato Semiconductor Corporation
2
01/01/10
POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
