Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Ansaldo Trasporti s.p.a.
Unita' Semiconduttori
ANSALDO
Tx 270318 ANSUSE I -
PHASE CONTROL THYRISTOR AT1007
Repetitive voltage up to
Mean on-state current
2400 V
1270 A
19 kA
Surge current
FINAL SPECIFICATION
feb 97 - ISSUE : 06
Tj
[°C]
Symbol
Characteristic
Conditions
Value
Unit
BLOCKING
V RRM
V RSM
V DRM
I RRM
I DRM
Repetitive peak reverse voltage
Non-repetitive peak reverse voltage
Repetitive peak off-state voltage
Repetitive peak reverse current
Repetitive peak off-state current
125 2400
125 2500
125 2400
V
V
V
V=VRRM
V=VDRM
125
125
50
50
mA
mA
CONDUCTING
I T (AV)
I T (AV)
I TSM
I² t
Mean on-state current
Mean on-state current
Surge on-state current
I² t
180° sin, 50 Hz, Th=55°C, double side cooled
180° sin, 50 Hz, Tc=85°C, double side cooled
sine wave, 10 ms
1270
1035
19
A
A
125
kA
without reverse voltage
1805 x1E3
2
A²s
V
V T
On-state voltage
On-state current = 2900 A
25
V T(TO)
r T
Threshold voltage
On-state slope resistance
125
1.15
V
125 0.308
mohm
SWITCHING
di/dt
dv/dt
td
Critical rate of rise of on-state current, min. From 75% VDRM up to 1350 A, gate 10V 5ohm 125
200
500
1.3
A/µs
V/µs
µs
Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM
125
25
Gate controlled delay time, typical
Circuit commutated turn-off time, typical
Reverse recovery charge
VD=100V, gate source 25V, 10 ohm , tr=.5 µs
tq
dV/dt = 20 V/µs linear up to 75% VDRM
di/dt=-20 A/µs, I= 880 A
VR= 50 V
320
µs
Q rr
I rr
I H
125
µC
A
Peak reverse recovery current
Holding current, typical
VD=5V, gate open circuit
VD=5V, tp=30µs
25
25
300
700
mA
mA
I L
Latching current, typical
GATE
V GT
Gate trigger voltage
VD=5V
25
25
3.5
300
0.25
30
V
mA
V
I GT
Gate trigger current
VD=5V
V GD
V FGM
Non-trigger gate voltage, min.
Peak gate voltage (forward)
Peak gate current
VD=VDRM
125
V
I
FGM
10
A
V RGM
P GM
P G
Peak gate voltage (reverse)
Peak gate power dissipation
Average gate power dissipation
5
V
Pulse width 100 µs
150
2
W
W
MOUNTING
R th(j-h)
Thermal impedance, DC
Thermal impedance
Junction to heatsink, double side cooled
Case to heatsink, double side cooled
26
6
°C/kW
°C/kW
R th(c-h)
T j
F
Operating junction temperature
Mounting force
-30 / 125
18.0 / 20.0
500
°C
kN
g
Mass
ORDERING INFORMATION : AT1007 S 24
VDRM&VRRM/100
standard specification
POSEICO [ POWER SEMICONDUCTORS ]
