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AT1004S16 参数 Datasheet PDF下载

AT1004S16图片预览
型号: AT1004S16
PDF下载: 下载PDF文件 查看货源
内容描述: 相位控制晶闸管 [PHASE CONTROL THYRISTOR]
分类和应用:
文件页数/大小: 4 页 / 171 K
品牌: POSEICO [ POWER SEMICONDUCTORS ]
 浏览型号AT1004S16的Datasheet PDF文件第2页浏览型号AT1004S16的Datasheet PDF文件第3页浏览型号AT1004S16的Datasheet PDF文件第4页  
POSEICO SPA  
Via N. Lorenzi 8, 16152 Genova - ITALY  
Tel. ++ 39 010 6556234 - Fax ++ 39 010 6557519  
Sales Office:  
POSEICO  
POSEICO SPA  
POwer SEmiconductors Italian COrporation  
Tel. ++ 39 010 6556775 - Fax ++ 39 010 6442510  
PHASE CONTROL THYRISTOR  
AT1004  
Repetitive voltage up to  
Mean on-state current  
Surge current  
1600 V  
1545 A  
24.6 kA  
FINAL SPECIFICATION  
feb 97 - ISSUE : 06  
Tj  
Symbol  
Characteristic  
Conditions  
Value  
Unit  
[°C]  
BLOCKING  
V RRM  
V RSM  
V DRM  
I RRM  
I DRM  
Repetitive peak reverse voltage  
Non-repetitive peak reverse voltage  
Repetitive peak off-state voltage  
Repetitive peak reverse current  
Repetitive peak off-state current  
125  
125  
125  
125  
125  
1600  
1700  
1600  
50  
V
V
V
mA  
mA  
V=VRRM  
V=VDRM  
50  
CONDUCTING  
I T (AV)  
I T (AV)  
I TSM  
I² t  
Mean on-state current  
Mean on-state current  
Surge on-state current  
I² t  
180° sin, 50 Hz, Th=55°C, double side cooled  
180° sin, 50 Hz, Tc=85°C, double side cooled  
sine wave, 10 ms  
1545  
1255  
24.6  
3026 x1E3  
1.63  
A
A
kA  
A²s  
V
125  
without reverse voltage  
V T  
On-state voltage  
On-state current =  
2900 A  
25  
V T(TO)  
r T  
Threshold voltage  
On-state slope resistance  
125  
125 0.216  
0.92  
V
mohm  
SWITCHING  
di/dt  
dv/dt  
td  
Critical rate of rise of on-state current, min.  
Critical rate of rise of off-state voltage, min.  
Gate controlled delay time, typical  
Circuit commutated turn-off time, typical  
Reverse recovery charge  
From 75% VDRM up to 1650 A, gate 10V 5ohm  
Linear ramp up to 70% of VDRM  
VD=100V, gate source 25V, 10 ohm , tr=.5 µs  
dV/dt = 20 V/µs linear up to 75% VDRM  
di/dt=-20 A/µs, I= 1080 A  
VR= 50 V  
VD=5V, gate open circuit  
VD=5V, tp=30µs  
125  
125  
25  
200  
500  
1.1  
A/µs  
V/µs  
µs  
µs  
µC  
A
tq  
250  
Q rr  
I rr  
I H  
125  
Peak reverse recovery current  
Holding current, typical  
25  
25  
300  
700  
mA  
mA  
I L  
Latching current, typical  
GATE  
V GT  
I GT  
Gate trigger voltage  
Gate trigger current  
Non-trigger gate voltage, min.  
Peak gate voltage (forward)  
Peak gate current  
VD=5V  
VD=5V  
VD=VDRM  
25  
25  
125  
3.5  
300  
0.25  
30  
V
mA  
V
V
A
V GD  
V FGM  
I
FGM  
10  
V RGM  
P GM  
P G  
Peak gate voltage (reverse)  
Peak gate power dissipation  
Average gate power dissipation  
5
150  
2
V
W
W
Pulse width 100 µs  
MOUNTING  
R th(j-h)  
R th(c-h)  
Thermal impedance, DC  
Thermal impedance  
Junction to heatsink, double side cooled  
Case to heatsink, double side cooled  
26  
6
°C/kW  
°C/kW  
T j  
F
Operating junction temperature  
Mounting force  
Mass  
-30 / 125  
18.0 / 20.0  
500  
°C  
kN  
g
ORDERING INFORMATION : AT1004 S 16  
VDRM&VRRM/100  
standard specification