RM9200A
Released
Integrated Multiprocessor
FEATURES
PMC-Sierra’s RM9200A Integrated
Processor is a high performance 64-bit
MIPS-based dual-microprocessor with
integrated memory and I/O interfaces.
The highly integrated RM9200A
addresses the expanding performance
and bandwidth requirements of these
markets with the following features,
specificically designed to enhance
networking:
• Dual 1 GHz E9000 cores compatible
with the MIPS64 instruction set
architecture.
• 512 Kbytes total of integrated L2
cache.
• TSMC 0.13
µm
high performance
copper process.
• 12 Watts (typical) power consumption.
• High speed integrated DDR SDRAM,
HyperTransport, SysAD and local bus
interfaces.
DUAL E9000 CORES
Each core provides:
• 1 GHz operating frequency.
• 16-Kbyte, 4-way set associative L1
Instruction and Data caches.
• 256-Kbyte, 4-way set associative L2
cache with deterministic access time
for highest performance.
• Fast Packet Cache to assist packet
data processing.
• An 8K entry branch prediction table.
• A dual issue superscalar 7-stage
pipeline.
• A fully associative 64-Entry TLB with
Dual Pages.
• Multiple reads with out of order return.
• A high performance Floating Point Unit
(IEEE 754).
• Fixed-point DSP instructions.
CACHE AND I/O COHERENCY
• Maintains hardware cache coherency
with the 5-state MOESI protocol. All
cache transfers between E9000 cores
occur at the CPU pipeline frequency.
• Supports full hardware I/O coherency
over the HyperTransport and SysAD
interfaces, allowing I/O devices access
to coherent memory.
• Provides Direct Deposit mode to allow
DMA of packet headers directly into L2
cache over the HyperTransport bus.
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sd
ay
128 GBPS MULTI-PORT SHARED
MEMORY FABRIC
• Connects E9000 CPU cores to
memory and I/O interfaces.
• Supports simultaneous transfers on
any port.
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2D
ec
BLOCK DIAGRAM
ilic
on
ex
p
er
lo
fs
E9000
Core
to
n
Th
ur
E9000
Core
ti
sm
ae
EJTAG
CPU Switch
Local Bus
za
Lo
Bu
cal
8
s
Kbyte
Shared Memory Fabric
DDR SDRAM
Controller
Scratch RAM
DMA
Controller
Coherent
Interconnect
Port
Coherent
Interconnect
Port
ed
by
ez
Do
PMC-2040956 (R2)
wn
lo
ad
HyperTransport
I/O Controller
SysAD
Controller
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
be
r,
200 MHZ DDR SDRAM MEMORY
CONTROLLER
• Supports 25.6 Gbps memory
bandwidth.
• Supports DDR SDRAM.
• Supports 2 Gbytes using 512 Mbit
SDRAM.
500 MHZ HYPERTRANSPORT
INTERFACE
• Supports 16 Gbps aggregate
bandwidth.
Interrupt
Controller
20
04
05
:3
2:
© Copyright PMC-Sierra, Inc. 2004
51
AM
PMC [ PMC-SIERRA, INC ]
