RM7035C/RM7065C
Microprocessors
Preliminary
64-Bit MIPS RISC Microprocessors with Integrated L2 Cache
FEATURES
• Dual issue symmetric superscalar
microprocessor with instruction
prefetch optimized for system level
price/performance:
•
466, 533, 600 MHz operating
frequency.
•
>1380 Dhrystone 2.1 MIPS @
600 MHz.
• High-performance system interface:
•
1600 Mbyte/s peak throughput.
•
200 MHz maximum frequency using
HSTL signaling on the SysAD bus.
•
Multiplexed address/data (SysAD)
bus supports 1.5 V, 2.5 V, 3.3 V I/O
logic.
•
Processor clock multipliers 2, 2.5, 3,
3.5, 4, 4.5, 5, 6, 7, 8, 9.
•
Support for 64- or 32-bit interfaces.
• Integrated primary and secondary
caches:
•
All are 4-way set associative with
32-byte line size.
16 Kbytes instruction, 16 Kbytes
data, 256 Kbytes on-chip
secondary.
•
Per line cache locking in primaries
and secondary.
•
Fast Packet Cache™ increases
system efficiency in networking
applications.
• High-performance floating-point unit -
1600 MFLOPS maximum:
•
Single cycle repeat rate for common
single-precision operations and
some double-precision operations.
•
Single cycle repeat rate for single-
precision combined multiply-add
operations.
•
Two cycle repeat rate for double-
precision multiply and double-
precision combined multiply-add
operations.
• MIPS IV superset instruction set
architecture:
•
Data PREFETCH instruction allows
the processor to overlap cache miss
latency and instruction execution.
•
Single-cycle floating-point multiply-
add.
• Integrated memory management unit:
•
Fully associative joint TLB (shared
by I and D translations).
•
64/48 dual entries map 128/96
pages.
•
Variable page size.
• Embedded application enhancements:
•
Specialized DSP integer Multiply-
Accumulate instructions,
(MAD/MADU) and three-operand
multiply instruction (MUL).
•
I&D Test/Break-point (Watch)
registers for emulation & debug.
•
Performance counter for system
and software tuning & debug.
•
14 fully prioritized vectored
interrupts - 10 external, 2 internal, 2
software.
•
Device
RM7035C
RM7065C
CPU Frequency
(MHz)
466,533,600
466,533,600
I/D Cache
16KB/16KB
16KB/16KB
Integrated
L2 Cache
Support
256 KB
256 KB
External
Bus
Width
32-bit
64-bit
External Bus
Frequency
(MHz)
200
200
VccInt
(V)
1.3
1.3
VccIO
(V)
2.5/3.3
2.5/3.3
Package
128-ExposedPad™
256-TBGA or
216-ExposedPad™
BLOCK DIAGRAM
64-bit Integer Unit
Dual-Issue
Superscalar
Integer Multiplier
System Control
PC Unit
64-bit Floating-Point Unit
Double / Single
IEEE 754
Instruction Dispatch
Instruction Cache
16 KB, 4-way, lockable
Memory Management Unit
Fully Associative
48 or 64 Entry
Data Cache
16 KB, 4-way, lockable
Bus Interface Unit
32-bit (RM7035C)
32/64-bit (RM7065C)
SysAD Bus
Interrupt Controller
System Cache (L2)
256 KB, 4-way, lockable
NMI, INT9 – INT0
PMC-2020578
Issue 2
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2003
All rights reserved.
PMC [ PMC-SIERRA, INC ]
