Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Revision History
Issue Number
Issue Date
Details Of Change
1
2
March 2000
July 2000
Creation of document
Added HSTL Power Dissipation values, corrected programming
constraints for EPP, added OOB, JTAG and PLL blocks to device
dataflow diagrams, added heat sink information to Characteristics
section, corrected EPP register section, corrected Frame Format
tables, added correct bit definition for EPP Interrupt register,
corrected diagram in Appendix C, added send and receive
procedure for control packets, added ESOBLCP register
explanation, corrected conditions in Table 57, corrected Scheduler
Refresh Procedure, added new drawing for Crossbar data flow,
corrected token explanation, corrected Figures 36 and 37,
corrected spelling and formatting errors throughout document.
3
August 2001
Removed bit 17 from Scheduler Status Register, updated BP_FIFO
information in Scheduler Control and Reset Register, corrected
bottom view drawings for Scheduler and Crossbar, corrected signal
description section in Scheduler and Crossbar for power pins,
corrected tper3, and tpl3 in AC Electrical, added memory address
information in EPP registers, corrected mechanical drawings,
updated state diagram in Scheduler, added information about
Scheduler PLL timing, updated initialization sequence for all chips,
corrected Dataslice Signal Description for ibpen0, added bit 14(13th
and 14th Dataslice enable) to EPP Control register, updated TDM
constraints, added Output TDM Queue Overflow to the EPP’s
Interrupt register, updated EPP Output Backpressure /
Unbackpressure Threshold register, updated LCS2 link
synchronization in appendix, modified EPP Egress Control Packet
Data Format table, Modified ETT1 usage of LCS2 protocol section
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
