Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 11. An ETT1 Port Operating in Subport Mode with Four OC-48c Linecards
ETT1 Port board
ETT1 Port board
OC-48c 0
OC-48c 1
OC-48c 2
OC-48c 3
Crossbar
Crossbar
Dataslice 0/1
Dataslice 0/1
Dataslice 0/1
Dataslice 0/1
Dataslice 0/1
Dataslice 0/1
Crossbar
Crossbar
Crossbar
Crossbar
25M cell/s
interface
Scheduler
EPP
Flow Control
Crossbar
The EPP can support all four best-effort priorities when operating in subport mode. This is the primary
feature that differentiates the EPP from the PP. Furthermore, the EPP can operate in a mixed mode switch,
so an ETT1 switch can have some ports operating in subport mode (quad OC-48c), while other ports
operate in normal mode (OC-192c).
NOTE: The EPP has been designed to operate with the same Dataslice device as the PP, and this
has certain limitations that the designer should be aware of. The following sections on
subporting explain these limitations.
Ports are numbered 0 through 31and each port has one EPP. Subports are denoted as 0 through 3. Ports
with subports are shown as a (port, subport) pair; for example, port 4, subport 3 would be shown as (4,3)
Ports without subports (OC-192c) are simply numbered. The following queueing description assumes an
ETT1 core configured with all 32 ports in subport mode, supporting 128 OC-48c linecards.
First, consider a single priority. Figure 12 shows the 128 counters needed by one OC-48c linecard. There
are currently two requests outstanding for output (0,0). The ETT1 Chip Set uses virtual output queues to
avoid head-of-line blocking issues, therefore, the EPP needs to keep track of unicast requests going to
each one of the 128 possible output channels (0,0) through (31,3). Consequently, 128 counters are
needed. These counters reflect the outstanding requests that this one OC-48c ingress linecard has made
to the switch.
34
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE