RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
The arbiter has a number of control registers which are used primarily for diagnostics. Except for initial
configuration after reset, the arbiter does not require any intervention from the OOB CPU.
5.1.3 OOB Interface and Control/Status Registers
All of the devices have an OOB interface. This interface allows a single local CPU to control and monitor all
of the devices within a core fabric. Internally, each device provides registers that can be mapped into the
CPU’s address space. These registers are described in more detail in Section 5.4 “Scheduler Registers”.
5.1.4 TDM Service
At every cell time the Scheduler may receive a TDM request from each port that intends to transfer a TDM
cell (according to the TDM tables in the Port Processor). If a TDM request is received then the Scheduler
will return a TDM Grant to that port, and that port will not be used in the arbitration of the best-effort traffic
for that cell time.
The Scheduler may also receive notification that a port is expecting to receive a TDM cell. This notification
identifies the port that will source the TDM cell. If the Scheduler receives a TDM request from the
designated source port then the destination port will receive an appropriate routing tag. However, if the
source port has not made a TDM request then the destination port will be eligible to receive a best-effort
cell.
The Scheduler is the point of synchronization for the TDM service provided by the core fabric. The TDM
control block generates synchronization signals at regular intervals. The period of these signals is
determined either by internal registers, or by signals received from an EPP. The Scheduler sends the
synchronization pulses to all 32 EPPs at the same time to indicate the start of a new TDM frame. See
Section 1.2.5 “TDM Service” on page 22 for more information on the TDM service.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE