Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 42. Simple Redundant Crossbar Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 43. Simple Redundant Scheduler Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 44. ETT1 Signals and Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 45. AIB Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 46. AIB Control/Status Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 47. Request to Grant latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 48. ETT1 Event Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 49. Cell Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 50. Illustrating the Flow of Cells from the Linecard CPU to the ETT1 CPU . . . . . . . . . . . . . . . . 110
Figure 51. Loopback Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 52. Control Packet Exchange Between Linecard CPU and ETT1 CPU. . . . . . . . . . . . . . . . . . . 112
Figure 53. Testing the ETT1 Internal Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 54. Dataslice Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 55. Slicing of a Data Cell into Logical Dataslices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 56. Dataslice CBGA Package Dimensions - Top and Side Views . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 57. Dataslice CBGA Package Dimensions - Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 58. An ETT1 Port Operating in Sub-port Mode with Four OC-48c Linecards . . . . . . . . . . . . . . 152
Figure 59. Functional Diagram of LCS Enhanced Port Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 60. Enhanced Port Processor CBGA Package Dimensions - Top and Side Views. . . . . . . . . . 221
Figure 61. Enhanced Port Processor (EPP) CBGA Package Dimensions - Bottom View . . . . . . . . . . 222
Figure 62. The Basic Dataflow Through the Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 63. Crossbar CCGA Package Dimensions - Top and Side Views . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 64. Crossbar CCGA package Dimensions - Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 65. Scheduler Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 66. Port State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 67. Scheduler CCGA package Dimensions - Top and Side Views . . . . . . . . . . . . . . . . . . . . . . 288
Figure 68. Scheduler CCGA package Dimensions - Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 69. Setup and Hold for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (OOB Interface) . . . . . . . . 308
Figure 70. Rise and Fall Times for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (OOB Interface). . . . . 309
Figure 71. OOB Test Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 72. Setup and Hold for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (JTAG Interface). . . . . . . . 310
Figure 73. Rise and Fall Times for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (JTAG Interface) . . . . 310
Figure 74. JTAG Test Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 75. Setup and Hold for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (Serdes Interface) . . . . . . 311
Figure 76. Rise and Fall Times for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (Serdes Interface) . . . 311
Figure 77. Serdes Test Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 78. Setup and Hold for 200 Mbps HSTL (EPP/DS Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 79. Rise and Fall Times for 200 Mbps HSTL (EPP/DS Interface) . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 80. Class 1 HSTL Test Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 81. Setup and Hold for 800 Mbps STI (AIB Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 82. Rise and Fall Times for 800 Mbps STI (AIB Interfaces)) . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
viii
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
