NSE-8G™ Standard Product Data Sheet
Preliminary
Register 000H: NSE-8G Master Reset
Bit
Type
Function
Default
Bit 31
Bit 30
Bit 29:0
R/W
R/W
R
DRESET
ARESET
Unused
0
0
X
This register allows separate software reset of digital and analog circuitry on the NSE.
ARESET
The ARESET bit allows the analog circuitry in the NSE-8G to be reset under software
control. If the ARESET bit is a logic one, all the NSE-8G analog circuitry is held in reset.
ARESET must be held at logic one for at least 100us to ensure correct reset of the CSU. This
bit is not self-clearing. Therefore, a logic zero must be written to bring the NSE-8G out of
reset. Holding the NSE-8G in a reset state places it into a low power, analog stand-by mode.
A hardware reset clears the ARESET bit, thus negating the analog software reset.
DRESET
The DRESET bit allows the digital circuitry in the NSE-8G to be reset under software
control. If the DRESET bit is a logic one, all the NSE-8G digital circuitry is held in reset.
This bit is not self-clearing. Therefore, a logic zero must be written to bring the NSE-8G out
of reset. Holding the NSE-8G in a reset state places it into a low power, digital stand-by
mode. A hardware reset clears the DRESET bit, thus negating the digital software reset.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
58
PMC [ PMC-SIERRA, INC ]
