PM8374A
DualPHY 1G
Released
2-channel 933 Mbit/s to 1.25 Gbits/s Transceiver
FEATURES
GENERAL
• Two 933 Mbits/s to 1.25 Gbits/s IEEE
802.3-2000 Gigabit Ethernet and Fibre
Channel Physical Interfaces (FC-PI)
System Compliant Transceivers.
• Two secondary serial channels for
redundant system design.
• Integrated clock synthesis, clock
recovery, serializer/deserializer, built-
in self-test, 8B/10B codec and IEEE
802.3-2000 Gigabit Ethernet Physical
Coding Sublayer (PCS) logic.
• Rate matching via IDLE character
insertion and deletion capable of
compensating up to ±200 ppm of clock
difference between channels.
• Pin programmable or software
configurable operation using 2-pin
IEEE 802.3 MDC/MDIO serial
management interface.
• Supports pin-programmable hardware
only device configuration.
SERIAL INTERFACE
• High-speed outputs feature
programmable output current to
optimize drive distance and power -
directly drives 50 ohm (100 ohm
differential) systems.
• Integrated 100 ohm differential
resistive termination for a smaller
solution footprint, easier layout and
improved signal integrity.
• Direct AC coupled interface to copper
serial backplanes, optics and coaxial
cable.
• Low threshold receive differential input
threshold.
• Receive channel output clocks eliminate
the need for PLLs in interface ASICs
• 1.8 V and 2.5 V interoperable; 3.3 V
tolerant.
TEST FEATURES
• IEEE 1149.1 JTAG Boundary Scan
support.
• Built-in self-test (BIST) via internal packet
generator/checker.
• Per-channel control of serial and parallel
loopbacks.
• 8B/10B error counters.
PHYSICAL
• Ultra-low power operation using 0.18 um
CMOS technology.
• Thermally enhanced, 289-pin BGA
package, 19 mm x 19 mm.
• 1.8 V core and analog power.
• I/O voltage configurable as 2.5 V or
1.8 V.
• Designed to operate over a wide
temperature range (-40 to +85 °C) and is
suited for central office and outside plant
equipment.
PARALLEL INTERFACE
• Supports GMII and TBI (Ten-bit
Interface) standards.
• Single Data Rate (SDR) parallel
interface with synchronous receive
clock (clock forwarding).
• Half Rate Receive Clock Mode that
supports Dual Data Rate.
BLOCK DIAGRAM
Transmit Channel (1 of 2)
TXDx9:0]
TxChnEn[1:0]
Primary
Tx Channel
Serializer
PTDO_Px
PTDO_Nx
TXCKx
TxFIFO
PCS
8B/10B
Encoder
Secondary
Tx Channel
Serializer
STDO_Px
STDO_Nx
Parallel
Loopback
Receive Channel (1 of 2)
RxChnSel
Serial
Loopback
Primary
Rx Channel
Clock
Recovery
&
Deserializer
Secondary
Rx Channel
Clock
Recovery
&
Deserializer
RXDx[9:0]
RxFIFO
PCS
10B/8B
Decoder
Byte
Align
PRDI_Px
PRDI_Nx
RBCx0
RBCx1
SRDI_Px
SRDI_Nx
Local Clock
PLL
JTAG
Control/Status
MDIO
I/F
REFCLK
RESET
CV_DIS_EN
EN_SLPBK
DEC_ENC_EN
PRES
GEMOD
POEN
BMOD
MODE[1:0]
PLL_LOCK
DVAD[4:0]
TCK
TDI
TMS
TRST
TDO
PMC-2040215
Issue 2
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
MDIO
MDC
© Copyright PMC-Sierra, Inc. 2004.
All rights reserved.
PMC [ PMC-SIERRA, INC ]
