PM8358
QuadPHY 10GX
Preliminary
10GbE and 10GFC Compliant Transceiver
GENERAL
• 10 Gbit/s bi-directional standards
compliant transceiver.
• Four independent 1.2 - 3.2 Gbit/s
SERDES.
• IEEE 802.3ae (10GbE) compliant
including XAUI, XGXS, and XGMII.
• ANSI T11.2 (10 Gigabit & 2 Gigabit
Fibre Channel) compliant.
• Supports PCI Express, Infiniband,
Serial Rapid I/O, OC-48, OBSAI RP3,
and other high speed backplane
applications.
• Redundant XAUI links for working and
protect backplane architectures.
• Integrated crossbar switch enables
any port to any port configurations for
both parallel and serial interfaces.
PARALLEL I/O
SERIAL I/O
• Fully redundant high-speed serial I/O
channels for convenient switching to
redundant fabric.
• High-speed outputs with
programmable pre-emphasis to drive
longer backplanes.
• High-speed inputs with programmable
equalization to achieve superior bit-
error rates.
ep
te
m
• 4 x 8 bit, 4 x 10 bit, 32 bit, or 40 bit
Dual Data (DDR) parallel interface
• Adaptive timing provides improved TX
XGMII timing margin.
• Selectable source simultaneous or
source synchronous transmit and
receive parallel interfaces.
• Convenient output clock for user
friendly ASIC timing.
• Interoperates with the 1.5 V HSTL and
2.5 V SSTL_2 standards.
BLOCK DIAGRAM
QuadPHY-10GX
rtm
SL0P_P/SL0P_N
SL1P_P/SL1P_N
SL2P_P/SL2P_N
SL3P_P/SL3P_N
Serializer
in
TX Primary
XAUI Port
er
In
8B/10B
Encoder
co
n
Fr
id
ay
FIFO
,0
1S
TX Redundant
XAUI Port
SL0P_R/SL0N_R
SL1P_R/SL1N_R
SL2P_R/SL2N_R
SL3P_R/SL3N_R
Serializer
Pa
Adaptive
Sampler
8B/10B
Encoder
of
FIFO
VREF
m
DL0P_P/DL0P_N
DL1P_P/DL1P_N
DL2P_P/DL2P_N
DL3P_P/DL3P_N
tT
RX Primary
XAUI Port
en
Clock
Recovery
De-
serializer
& Byte
Align
C
r
o
s
s
b
a
r
10B/8B
Decoder
FIFO &
Trunking
ea
be
nt
DL0R_P/DL0R_N
Co
RX Redundant
XAUI Port
by
DL1R_P/DL1R_N
DL2R_P/DL2R_N
DL3R_P/DL3R_N
EN_SLPBK
SD_P
SD_R
Clock
Recovery
De-
serializer
& Byte
Align
10B/8B
Decoder
FIFO &
Trunking
ed
lo
ad
JTAG
Test Access Port
Management
Interface
Clock
Synthesizer
Common Control Logic
5
MDIO_SEL
MDIO
PRTAD[4:0]
MDC
SCAN_EN
TMS
SCANB
TCK
TRSTB
TDO
TDI
2
SYSCLK
REFCLK +/-
2
OSC +/-
3
RSTB
wn
2
HC[1:0]
EN_PRE-
EMPHASIS
MODE_SEL[2:0]
EN_EQUALIZA
TION
FAILOVER_IMM
FAILOVER
INTB
PMC-2020255
Issue 5
Do
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
r,
TRUNKING &TIMING
• Trunking feature de-skews and aligns
all four channels to form a single
10 Gbit/s logical link.
TX XGMII
TXD[31:0]]
TXC[3:0]
TXH[3:0]
TXCLK
RX XGMII
RXD[31:0]
RXC[3:0]
RXH[3:0]
RX_CLK_1
RX_CLK_1
RX_CLK_2
RX_CLK_3
RX_FAULT_P
RX_FAULT_R
TX_FAULT_P
TX_FAULT_R
20
06
02
:
© Copyright PMC-Sierra, Inc. 2003.
All rights reserved.
43
:4
8A
M
FEATURES
• Wide operating range from 1.2 Gbit/s -
3.2 Gbit/s enables backward
compatibility
• Integrated serializer/deserializer, clock
synthesis, clock recovery and 8B/10B
encode/decode logic.
• Bypass of 8B/10B encode/decode for
serialization of NRZ data streams.
• Pin configurable for standalone
operation.
• High-speed I/O with on-chip
termination resistors to directly drive
dual terminated 50 Ohm lines.
PMC [ PMC-SIERRA, INC ]
