PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
less than the transfer size will be naturally transferred to the RAPI672 block
without having to precisely track the number of full blocks in the channel FIFO.
The partial packet roamer performs the transaction accounting for all channel
FIFOs. The roamer increments the transaction count when the writer signals a
new transaction and sets a per-channel flag to indicate a non-zero transaction
count. The roamer searches the flags in a round-robin fashion to decide for
which channel FIFO to request transfer by the RAPI672 block. The roamer
informs the partial packet reader of the channel to process. The reader transfers
the data to the RAPI672 until the channel transfer size is reached or an end of
packet is detected. The reader then informs the roamer that a transaction is
consumed. The roamer updates its transaction count and clears the non-zero
transaction count flag if required. The roamer then services the next channel
with its transaction flag set high.
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets the
flag after the block is written and the reader clears the flag after the block is read.
The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The writer declares a channel FIFO overrun whenever the
writer tries to store data to a block with a set flag. In order to support optional
removal of the FCS from the packet data, the writer does not declare a block as
filled (set the block flag nor increment the transaction count) until the first double
word of the next block in channel FIFO is filled. If the end of a packet resides in
the first double word, the writer declares both blocks as full at the same time.
When the reader finishes processing a transaction, it examines the first double
word of the next block for the end-of-packet flag. If the first double word of the
next block contains only FCS bytes, the reader would, optionally, process next
transaction (end-of-packet) and consume the block, as it contains information not
transferred to the RAPI672 block.
8.6 Receive Any-PHY Interface
The Receive Any-PHY Interface (RAPI672) provides a low latency path for
transferring data out of the partial packet buffer in the RHDL672 and onto the
Receive Any-PHY Packet Interface (Rx APPI). The RAPI672 contains a FIFO
block for latency control as well as to segregate the APPI timing domain from the
SYSCLK timing domain. The RAPI672 contains the necessary logic to manage
and respond to device polling from an upper layer device. The RAPI672 also
provides the upper layer device with status information on a per packet basis.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
47
PMC [ PMC-SIERRA, INC ]
