PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Sꢀ For each channel, the HDLC transmitter supports programmable flag
sequence generation, bit stuffing and frame check sequence generation. The
transmitter supports the generation of both CRC-CCITT and CRC-32 frame
check sequences. The transmitter also aborts packets under the direction of
the external controller or automatically when the channel underflows.
Sꢀ Alternatively, for each channel, the transmitter supports a transparent mode
where each octet is inserted transparently from the transmit APPI. For
channelised links, the octets are aligned with the transmit time-slots.
Sꢀ Supports per-channel configurable APPI burst sizes of up to 256 bytes for
transfers of packet data.
Sꢀ The FREEDM maintains packet level performance metrics such as number of
received packets, number of received packets with frame check sequence
errors, number of transmitted packets, number of receive aborted packets,
and number of transmit aborted packets.
Sꢀ Provides 32 Kbytes of on-chip memory for partial packet buffering in both the
transmit and the receive directions. This memory may be configured to
support a variety of different channel configurations from a single channel with
32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of
buffering.
Sꢀ Provides a 16 bit microprocessor interface for configuration and status
monitoring.
Sꢀ Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
Sꢀ Supports 3.3 Volt tolerant I/O.
Sꢀ Low power 2.5 Volt 0.25 ꢁm CMOS technology.
Sꢀ 352 pin enhanced ball grid array (SBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2
PMC [ PMC-SIERRA, INC ]
