PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x100 : RCAS Indirect Link and Time-slot Select
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R/W
BUSY
RWB
X
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
Unused
LINK[6]
LINK[5]
LINK[4]
LINK[3]
LINK[2]
LINK[1]
LINK[0]
Unused
TSLOT[4]
TSLOT[3]
TSLOT[2]
TSLOT[1]
TSLOT[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 4
Bit 3
Bit 2
Bit 1
R/W
R/W
R/W
R/W
R/W
Bit 0
This register provides the receive link and time-slot number used to access the
channel provision RAM. Writing to this register triggers an indirect register
access.
TSLOT[4:0]:
The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be
configured or interrogated in the indirect access. For a channelised T1/J1
link, time-slots 1 to 24 are valid. For a channelised E1 link, time-slots 1 to 31
are valid. For unchannelised or unframed links, only time-slot 0 is valid.
LINK[6:0]:
The indirect link number bits (LINK[6:0]) select amongst the 84 receive links
to be configured or interrogated in the indirect access.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
94
PMC [ PMC-SIERRA, INC ]
