PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x3B0 : THDL Configuration
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXH
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
BIT8
TSTD
BURSTEN
Unused
Unused
0
0
0
X
X
X
0
0
0
0
Unused
R/W
R/W
R/W
R/W
BURST[3]
BURST[2]
BURST[1]
BURST[0]
This register configures all provisioned channels.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
BURST[3:0]:
The DMA burst length bits (BURST[3:0]) configure the maximum amount of
transmit data that can be requested in a single DMA transaction for channels
whose channel transfer size is set to one block (XFER[3:0] = 'b0000).
BURST[3:0] has no effect when BURSTEN is set low, nor on channels
configured with other transfer sizes. BURST[3:0] defines the maximum
number of 16 byte blocks, less one, that is transferred in each DMA
transaction. Thus, the minimum number of blocks is one (16 bytes) and the
maximum is sixteen (256 bytes).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
238
PMC [ PMC-SIERRA, INC ]
