PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
FPTR[10:0]:
The indirect FIFO block pointer (FPTR[10:0]) informs the partial packet buffer
processor the circular linked list of blocks to use for a FIFO for the channel.
The FIFO pointer to be written to the channel provision RAM, in an indirect
write operation, must be set up in this register before triggering the write. The
FIFO pointer value can be any one of the block numbers provisioned, by
indirect block write operations, to form the circular buffer.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM-
84P672 device.
DELIN:
The indirect delineate enable bit (DELIN) configures the HDLC processor to
perform flag sequence insertion and bit stuffing on the outgoing data stream.
The delineate enable bit to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. When DELIN is set high, flag sequence insertion, bit
stuffing and ,optionally, CRC generation is performed on the outgoing HDLC
data stream. When DELIN is set low, the HDLC processor does not perform
any processing (flag sequence insertion, bit stuffing nor CRC generation) on
the outgoing stream. DELIN reflects the value written until the completion of
a subsequent indirect channel read operation.
CRC[1:0]:
The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform
CRC generation on the outgoing HDLC data stream. The value of CRC[1:0]
to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. CRC[1:0]
is ignored when DELIN is low. CRC[1:0] reflects the value written until the
completion of a subsequent indirect channel read operation.
Table 32 – CRC[1:0] Settings
CRC[1]
CRC[0]
Operation
0
0
1
1
0
1
0
1
No CRC
CRC-CCITT
CRC-32
Reserved
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
224
PMC [ PMC-SIERRA, INC ]
