PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x330 : TMAC Descriptor Reference Ready Queue Read
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDRRQR[15]
TDRRQR[14]
TDRRQR[13]
TDRRQR[12]
TDRRQR[11]
TDRRQR[10]
TDRRQR[9]
TDRRQR[8]
TDRRQR[7]
TDRRQR[6]
TDRRQR[5]
TDRRQR[4]
TDRRQR[3]
TDRRQR[2]
TDRRQR[1]
TDRRQR[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the Transmit Descriptor Reference Ready Queue read
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
217
PMC [ PMC-SIERRA, INC ]
