PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
RPDRLFQW[15:0]:
The receive packet descriptor reference (RPDR) large buffer free queue write
bits (RPDRLFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Large Buffer Free Queue write pointer. This register is initialised
by the host. The physical write address in the RPDRLF queue is the sum of
RPDRLFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
174
PMC [ PMC-SIERRA, INC ]
