PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x28C : RMAC Packet Descriptor Table Base MSW
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RPDTB[31]
RPDTB[30]
RPDTB[29]
RPDTB[28]
RPDTB[27]
RPDTB[26]
RPDTB[25]
RPDTB[24]
RPDTB[23]
RPDTB[22]
RPDTB[21]
RPDTB[20]
RPDTB[19]
RPDTB[18]
RPDTB[17]
RPDTB[16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the more significant word of the Receive Descriptor Table
Base address. The contents of the companion RMAC Receive Descriptor Table
Base LSW register is held in a holding register until a write access to this
register, at which point, the base address of the receive packet descriptor table is
updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
166
PMC [ PMC-SIERRA, INC ]
