PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
LCACHE:
The large buffer cache enable bit (LCACHE) enables caching of Large Buffer
RPDRs. When LCACHE is set high, RPDRs are fetched from the RPDR
Large Buffer Free Queue in groups of up to six. When LCACHE is set low,
RPDRs are fetched one at a time.
SCACHE:
The small buffer cache enable bit (SCACHE) enables caching of Small Buffer
RPDRs. When SCACHE is set high, RPDRs are fetched from the RPDR
Small Buffer Free Queue in groups of up to six. When SCACHE is set low,
RPDRs are fetched one at a time.
RAWMAX[1:0]:
The RAWMAX[1:0] field determines how ‘raw’ (i.e. non packet delimited) data
is written to host memory. Raw data is written to buffers in host memory in
the same manner as packet delimited data. Whenever RAWMAX[1:0] + 1
buffers have been filled, the resulting buffer chain is placed in the ready
queue.
RPQ_RDYN[2:0]:
The RPQ_RDYN[2:0] field sets the number of receive packet descriptor
references (RPDRs) that must be placed onto the RPDR ready queue before
the RPDR ready interrupt (RPQRDYI) is asserted, as follows:
Table 27 – RPQ_RDYN[2:0] settings
RPQ_RDYN[2:0]
No of RPDRs
000
001
010
011
100
101
110
111
1
4
6
8
16
32
Reserved
Reserved
If the value of RPQ_RDYN[2:0] is altered, the new value does not become
effective until after the RPQRDYI interrupt is next generated.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
161
PMC [ PMC-SIERRA, INC ]
