RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
8.8.4 Channel Assigner
The channel assigner block determines the channel number of the request
currently being processed. The block contains a 1024 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the highest priority requester. The fields of
each RAM word include the channel number and a time-slot enable flag. The
time-slot enable flag labels the current time-slot as belonging to the channel
indicted by the channel number field. For time-slots that are enabled, the
channel assigner issues a request to the THDL256 block which responds with
packet data within one byte period of the transmit stream.
8.9 Performance Monitor
The Performance Monitor block (PMON) contains four counters. The first two
accumulate receive partial packet buffer FIFO overrun events and transmit partial
packet buffer FIFO underflow events, respectively. The remaining two counters
are software programmable to accumulate a variety of events, such as receive
packet count, FCS error counts, etc. All counters saturate upon reaching
maximum value. The accumulation logic consists of a counter and holding
register pair. The counter is incremented when the associated event is detected.
Writing to the FREEDM-32A256 Master Clock / BERT Activity Monitor and
Accumulation Trigger register transfer the count to the corresponding holding
register and clear the counter. The contents of the holding register is accessible
via the microprocessor interface.
8.10 JTAG Test Access Port Interface
The JTAG Test Access Port block provides JTAG support for boundary scan. The
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions
are supported. The FREEDM-32A256 identification code is 073830CD
hexadecimal.
8.11 Microprocessor Interface
The FREEDM-32A256 supports microprocessor access to an internal register
space for configuring and monitoring the device. All registers are 16 bits wide but
are DWORD aligned in the microprocessor memory map. The registers are
described below:
PROPRIETARY AND CONFIDENTIAL
64
PMC [ PMC-SIERRA, INC ]
