RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Table 17 – Test Mode Register Memory Map
Address TA[12:0]
Register
0x0000 - 0x07FE
0x0800 - 0x10FE
0x1100 - 0x11FE
0x1200 - 0x123E
0x1240 - 0x137E
0x1380 - 0x13BE
0x13C0 - 0x13FE
0x1400 - 0x14FE
0x1500 - 0x151E
0x1520 - 0x157E
0x1580 - 0x15BE
0x15C0 - 0x15FE
0x1600 - 0x163E
0x1640 - 0x1FFE
Normal Mode Registers
Reserved
RCAS256 Test Registers
RHDL256 Test Registers
Reserved
THDL256 Test Registers
Reserved
TCAS256 Test Registers
PMON Test Registers
Reserved
RAPI256 Test Registers
Reserved
TAPI256 Test Registers
Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software
compatibility with future, feature-enhanced versions of the product, unused register
bits must be written with logic zero. Reading back unused bits can produce either a
logic one or a logic zero; hence unused register bits should be masked off by
software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
10.2 JTAG Test Port
The FREEDM-32A256 JTAG Test Access Port (TAP) allows access to the TAP
controller and the 4 TAP registers: instruction, bypass, device identification and
boundary scan. Using the TAP, device input logic levels can be read, device
outputs can be forced, the device can be identified and the device scan path can
PROPRIETARY AND CONFIDENTIAL
160
PMC [ PMC-SIERRA, INC ]
