RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x508 : PMON Transmit FIFO Underflow Count
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
UF[15]
UF[14]
UF[13]
UF[12]
UF[11]
UF[10]
UF[9]
UF[8]
UF[7]
UF[6]
UF[5]
UF[4]
UF[3]
UF[2]
UF[1]
UF[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register reports the number of transmit FIFO underflow events in the
previous accumulation interval.
UF[15:0]:
The UF[15:0] bits reports the number of transmit FIFO underflow events that
have been detected since the last time this register was polled. This register
is polled by writing to the FREEDM-32A256 Master Clock / BERT Activity
Monitor and Accumulation Trigger register. The write access transfers the
internally accumulated error count to the FIFO underflow register and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
PROPRIETARY AND CONFIDENTIAL
148
PMC [ PMC-SIERRA, INC ]
