RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
16-byte blocks. XFER[3:0] reflects the value written until the completion of a
subsequent indirect channel read operation.
To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to
be less than or equal to the start transmission level set by LEVEL[3:0] and
TRANS. Alternatively, the channel transfer size can be set such that the total
number of blocks in the logical channel FIFO minus the start transmission
level is an integer multiple of the channel transfer size.
FLAG[2:0]:
The flag insertion control (FLAG[2:0]) configures the minimum number of
flags or bytes of idle bits the HDLC processor inserts between HDLC packets.
The value of FLAG[2:0] to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. The minimum number of flags or bytes of idle (8 bits of
1’s) inserted between HDLC packets is shown in the table below. FLAG[2:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
Table 13 – FLAG[2:0] Settings
FLAG[2:0] Minimum Number of Flag/Idle Bytes
000
001
010
011
100
101
110
111
1 flag / 0 Idle byte
2 flags / 0 idle byte
4 flags / 2 idle bytes
8 flags / 6 idle bytes
16 flags / 14 idle bytes
32 flags / 30 idle bytes
64 flags / 62 idle bytes
128 flags / 126 idle bytes
LEVEL[3:0]:
The indirect channel FIFO trigger level (LEVEL[3:0]), in concert with the
TRANS bit, configure the various channel FIFO free space levels which
trigger the HDLC processor to start transmission of a HDLC packet as well as
trigger the partial packet buffer to request data from the TAPI256 as shown in
the following table. The channel FIFO trigger level to be written to the
channel provision RAM, in an indirect write operation, must be set up in this
PROPRIETARY AND CONFIDENTIAL
125
PMC [ PMC-SIERRA, INC ]
