RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x004 : FREEDM-32A256 Master Interrupt Enable
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
R/W
R/W
R/W
R/W
TFUDRE
TFOVRE
TUNPVE
TPRTYE
Unused
0
0
0
0
XXH
Bit 11
to
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
RFOVRE
RPFEE
RABRTE
RFCSEE
Unused
Unused
0
0
0
0
X
X
This register provides interrupt enables for various events detected or initiated by
the FREEDM-32A256.
RFCSEE:
The receive frame check sequence error interrupt enable bit (RFCSEE)
enables receive FCS error interrupts to the microprocessor. When RFCSEE
is set high, a mismatch between the received FCS code and the computed
CRC residue will cause an interrupt to be generated on the INTB output.
Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit
remains valid when interrupts are disabled and may be polled to detect
receive FCS error events.
RABRTE:
The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort
interrupts to the microprocessor. When RABRTE is set high, receipt of an
abort code (at least 7 contiguous 1’s) will cause an interrupt to be generated
on the INTB output. Interrupts are masked when RABRTE is set low.
PROPRIETARY AND CONFIDENTIAL
71
PMC [ PMC-SIERRA, INC ]
