RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Table 8 – Normal Mode Microprocessor Accessible Registers
Address
Register
0x000
0x004
0x008
0x00C
FREEDM-32A256 Master Reset
FREEDM-32A256 Master Interrupt Enable
FREEDM-32A256 Master Interrupt Status
FREEDM-32A256 Master Clock / Frame Pulse / BERT
Activity Monitor and Accumulation Trigger
0x010
0x014
0x018
0x01C
0x020
0x024
FREEDM-32A256 Master Link Activity Monitor
FREEDM-32A256 Master Line Loopback #1
FREEDM-32A256 Master Line Loopback #2
FREEDM-32A256 Reserved
FREEDM-32A256 Master BERT Control
FREEDM-32A256 Master Performance Monitor Control
0x028 – 0x0FC Reserved
0x100
RCAS Indirect Channel and Time-slot Select
0x104
0x108
0x10C
0x110 – 0x17C
RCAS Indirect Channel Data
RCAS Framing Bit Threshold
RCAS Channel Disable
RCAS Reserved
0x180 – 0x1FC RCAS Link #0 through #31 Configuration
0x200
0x204
0x208
0x20C
RHDL Indirect Channel Select
RHDL Indirect Channel Data Register #1
RHDL Indirect Channel Data Register #2
RHDL Reserved
0x210
0x214
0x218 – 0x21C
0x220
RHDL Indirect Block Select
RHDL Indirect Block Data Register
RHDL Reserved
RHDL Configuration
0x224
RHDL Maximum Packet Length
PROPRIETARY AND CONFIDENTIAL
65
PMC [ PMC-SIERRA, INC ]
