RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
8.6.2 Polling Control and Management
The TAPI256 only responds to poll addresses which are in the range
programmed in the base address field in the TAPI256 Control register. The
TAPI256 uses the 3 most significant bits of the poll address for device recognition
and the 10 least significant bits of the poll address for identification of a channel.
The TAPI256 provides three poll results for every poll address according to Table
7. The TPAn[0] bit indicates whether or not space exists in the channel FIFO for
data and the TPAn[1] bit indicates whether or not that polled channel FIFO is at
risk of underflowing and should be provided data soon. The TPAn[2] bit indicates
that an underflow event has occurred on that channel FIFO.
Table 7 – Transmit Polling
Poll
TPA1[0]
TPA1[1]
TPA1[2]
TPA2[0]
TPA2[1]
TPA2[2]
Address
(Full/Space)
(Space/Starving)
(Full/Space)
(Space/Starving)
(Underflow)
(Underflow)
Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1
Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2
Channel 2 Channel 2 Channel 2 Channel 2 Channel 3 Channel 3 Channel 3
Channel 3 Channel 3 Channel 3 Channel 3 Channel 4 Channel 4 Channel 4
Channel 4 Channel 4 Channel 4 Channel 4 Channel 5 Channel 5 Channel 5
Channel 5 Channel 5 Channel 5 Channel 5 Channel 6 Channel 6 Channel 6
Channel 6 Channel 6 Channel 6 Channel 6 Channel 7 Channel 7 Channel 7
Channel 7 Channel 7 Channel 7 Channel 7 Channel 8 Channel 8 Channel 8
Channel 8 Channel 8 Channel 8 Channel 8 Channel 9 Channel 9 Channel 9
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
Channel
255
Channel
255
Channel
255
Channel Channel 0 Channel 0 Channel 0
255
The TAPI256 maintains a mirror image of the status of each channel FIFO in the
partial packet buffer. The THDL256 continuously reports the status of the 256
channel FIFOs to the TAPI256 and the TAPI256 updates the mirror image
accordingly. The THDL256 also signals to the TAPI256 whenever an underflow
event has occurred on a channel FIFO. At the beginning of every data transfer
across the Tx APPI, the TAPI256 sets the mirror image status of the channel to
“full”. Only the TAPI256 can cause the status to be set to “full” and only the
THDL256 can cause the status to be set to “space” or “starving”. Only the
THDL256 can cause the status to be set to “underflow” and only the TAPI256 can
clear the “underflow” status when that channel FIFO is polled. In the event that
PROPRIETARY AND CONFIDENTIAL
56
PMC [ PMC-SIERRA, INC ]
