RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Table 2 – Any-PHY Packet Interface Signals (70)
Pin Name
Type
Pin
No.
Function
TXCLK
Input
H2
The transmit clock signal (TXCLK) provides
timing for the transmit Any-PHY packet
interface. TXCLK is a nominally 50% duty
cycle, 25 to 50 MHz clock.
TXADDR[0]
TXADDR[1]
TXADDR[2]
TXADDR[3]
TXADDR[4]
TXADDR[5]
TXADDR[6]
TXADDR[7]
TXADDR[10]
TXADDR[11]
TXADDR[12]
Input
H1
G3
G2
G4
G1
F2
F1
F3
D2
D1
E4
The transmit address signals (TXADDR[12:0])
provide a channel address for polling a transmit
channel FIFO. The 8 least significant bits
provide the channel number (0 to 255) while the
3 most significant bits select one of seven
possible FREEDM-32A256 devices sharing a
single external controller. (One address is
reserved as a null address.) The Tx APPI of
each FREEDM-32A256 device is identified by
the base address in the TAPI256 Control
register.
The TXADDR[12:0] signals are sampled on the
rising edge of TXCLK.
Note that TXADDR[9:8] have been removed
from the FREEDM-32A256 device. Pin
numbering of TXADDR[7:0] and
TXADDR[12:10] has been maintained to allow
software compatibility with the FREEDM-
32A672 device.
PROPRIETARY AND CONFIDENTIAL
23
PMC [ PMC-SIERRA, INC ]
