RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
CONTENTS
1
2
3
4
5
6
7
8
FEATURES...............................................................................................1
APPLICATIONS........................................................................................4
REFERENCES .........................................................................................5
BLOCK DIAGRAM....................................................................................6
DESCRIPTION .........................................................................................7
PIN DIAGRAM........................................................................................11
PIN DESCRIPTION ................................................................................12
FUNCTIONAL DESCRIPTION................................................................44
8.1
HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL
(H-MVIP)......................................................................................44
8.2
8.3
HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........44
RECEIVE CHANNEL ASSIGNER................................................45
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Line Interface Translator (LIT) .......................................47
Line Interface.................................................................48
Priority Encoder .............................................................48
Channel Assigner ..........................................................49
Loopback Controller.......................................................49
8.4
8.5
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...49
8.4.1
8.4.2
HDLC Processor............................................................50
Partial Packet Buffer Processor.....................................50
RECEIVE ANY-PHY INTERFACE................................................52
8.5.1
FIFO Storage and Control..............................................53
PROPRIETARY AND CONFIDENTIAL
i