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PM7383 参数 Datasheet PDF下载

PM7383图片预览
型号: PM7383
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
CONTENTS  
1
2
3
4
5
6
7
8
FEATURES...............................................................................................1  
APPLICATIONS........................................................................................4  
REFERENCES .........................................................................................5  
BLOCK DIAGRAM....................................................................................6  
DESCRIPTION .........................................................................................7  
PIN DIAGRAM........................................................................................11  
PIN DESCRIPTION ................................................................................12  
FUNCTIONAL DESCRIPTION................................................................44  
8.1  
HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL  
(H-MVIP)......................................................................................44  
8.2  
8.3  
HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........44  
RECEIVE CHANNEL ASSIGNER................................................45  
8.3.1  
8.3.2  
8.3.3  
8.3.4  
8.3.5  
Line Interface Translator (LIT) .......................................47  
Line Interface.................................................................48  
Priority Encoder .............................................................48  
Channel Assigner ..........................................................49  
Loopback Controller.......................................................49  
8.4  
8.5  
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...49  
8.4.1  
8.4.2  
HDLC Processor............................................................50  
Partial Packet Buffer Processor.....................................50  
RECEIVE ANY-PHY INTERFACE................................................52  
8.5.1  
FIFO Storage and Control..............................................53  
PROPRIETARY AND CONFIDENTIAL  
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