RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
12.3 Receive non H-MVIP Link Timing
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
an unchannelised link is shown in Figure 16. The receive data is viewed as a
contiguous serial stream. There is no concept of time-slots in an unchannelised
link. Every eight bits are grouped together into a byte with arbitrary alignment.
The first bit received (B1 in Figure 16) is deemed the most significant bit of an
octet. The last bit received (B8) is deemed the least significant bit. Bits that are
to be processed by the FREEDM-32A256 are clocked in on the rising edge of
RCLK[n]. Bits that should be ignored (X in Figure 16) are squelched by holding
RCLK[n] quiescent. In Figure 16, the quiescent period is shown to be a low level
on RCLK[n]. A high level, effected by extending the high phase of the previous
valid bit, is also acceptable. Selection of bits for processing is arbitrary and is not
subject to any byte alignment nor frame boundary considerations.
Figure 16 – Unchannelised Receive Link Timing
RCLK[n]
B1 B2 B3 B4 X B5 X
X X B6 B7 B8 B1 X
RD[n]
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
a channelised T1/J1 link is shown in Figure 17. The receive data stream is a
T1/J1 frame with a single framing bit (F in Figure 17) followed by octet bound
time-slots 1 to 24. RCLK[n] is held quiescent during the framing bit. The RD[n]
data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the
framing bit is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS24)
clocked in by the last rising edge of RCLK[n] before the framing bit is the least
significant bit of time-slot 24. In Figure 17, the quiescent period is shown to be a
low level on RCLK[n]. A high level, effected by extending the high phase of bit
B8 of time-slot TS24, is equally acceptable. In channelised T1/J1 mode,
RCLK[n] can only be gapped during the framing bit. It must be active
continuously at 1.544 MHz during all time-slot bits. Time-slots can be ignored by
setting the PROV bit in the corresponding word of the receive channel provision
RAM in the RCAS256 block to low.
PROPRIETARY AND CONFIDENTIAL
190
PMC [ PMC-SIERRA, INC ]
