RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
processing it. The value of INVERT to be written to the channel provision
RAM, in an indirect channel write operation, must be set up in this register
before triggering the write. When INVERT is set to one, the HDLC stream is
logically inverted before processing. When INVERT is set to zero, the HDLC
stream is not inverted before processing. INVERT reflects the value written
until the completion of a subsequent indirect channel read operation.
PRIORITY:
The channel FIFO priority bit (PRIORITY) informs the partial packet processor
that the channel has precedence over other channels when being serviced by
the RAPI256 block for transfer across the receive APPI. The value of
PRIORITY to be written to the channel provision RAM, in an indirect channel
write operation, must be set up in this register before triggering the write.
Channel FIFOs with PRIORITY set to one are serviced by the RAPI256
before channel FIFOs with PRIORITY set to zero. Channels with an HDLC
data rate to FIFO size ratio that is significantly higher than other channels
should have PRIORITY set to one. PRIORITY reflects the value written until
the completion of a subsequent indirect channel read operation.
7BIT:
The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least
significant bit of each octet in the corresponding link RD[n]. The value of 7BIT
to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. When
7BIT is set high, the least significant bit (last bit of each octet received), is
ignored. When 7BIT is set low, the entire receive data stream is processed.
7BIT reflects the value written until the completion of a subsequent indirect
channel read operation.
PROPRIETARY AND CONFIDENTIAL
110
PMC [ PMC-SIERRA, INC ]
