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PM7383 参数 Datasheet PDF下载

PM7383图片预览
型号: PM7383
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
supports the validation of both CRC-CCITT and CRC-32 frame check  
sequences.  
Sꢀ For each channel, the receiver checks for packet abort sequences, octet  
aligned packet length and for minimum and maximum packet length. The  
receiver supports filtering of packets that are larger than a user specified  
maximum value.  
Sꢀ Alternatively, for each channel, the receiver supports a transparent mode  
where each octet is transferred transparently on the receive APPI. For  
channelised links, the octets are aligned with the receive time-slots.  
Sꢀ For each channel, time-slots are selectable to be in 56 kbits/s format or 64  
kbits/s clear channel format.  
Sꢀ For each channel, the HDLC transmitter supports programmable flag  
sequence generation, bit stuffing and frame check sequence generation. The  
transmitter supports the generation of both CRC-CCITT and CRC-32 frame  
check sequences. The transmitter also aborts packets under the direction of  
the external controller or automatically when the channel underflows.  
Sꢀ Alternatively, for each channel, the transmitter supports a transparent mode  
where each octet is inserted transparently from the transmit APPI. For  
channelised links, the octets are aligned with the transmit time-slots.  
Sꢀ Supports per-channel configurable APPI burst sizes of up to 256 bytes for  
transfers of packet data.Provides 32 Kbytes of on-chip memory for partial  
packet buffering in both the transmit and the receive directions. This memory  
may be configured to support a variety of different channel configurations  
from a single channel with 32 Kbytes of buffering to 256 channels, each with a  
minimum of 48 bytes of buffering.  
Sꢀ Provides a 16 bit microprocessor interface for configuration and status  
monitoring.  
Sꢀ Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board  
test purposes.  
Sꢀ Supports 5 Volt tolerant I/O (except APPI).  
Sꢀ Low power 2.5 Volt 0.25 m CMOS technology.  
PROPRIETARY AND CONFIDENTIAL  
2