PM7382
FREEDM-32P256
Frame Engine and Data Link Manager 32P256
OVERVIEW
The FREEDM-32P256 chip offers the
following features:
• Single-chip multi-channel HDLC
controller with a 66 MHz, 32-bit
Peripheral Component Interconnect
(PCI) 2.1 compatible bus for
configuration, monitoring, and transfer
of packet data.
• An on-chip DMA controller with
scatter/gather capabilities.
• Supports up to 256 bi-directional
HDLC channels assigned to a
maximum of 32 channelized T1/J1/E1
links. You can program the number of
time-slots assigned to an HDLC
channel from 1 to 24 (for T1/J1) and
from 1 to 31 (for E1).
• Supports up to 256 bi-directional
HDLC channels assigned to a
maximum of 32 MVIP digital telephony
buses at 2.048 Mbit/s per link, or
8 H-MVIP buses at 8.192 Mbit/s per
link.
• Supports up to 32 bi-directional HDLC
channels, each assigned to an
unchannelized arbitrary-rate link,
subject to a maximum aggregate link
clock-rate of 64 MHz in each direction.
• Channels assigned to links 0 to 2
support clock rates up to 52 MHz.
Channels assigned to links 3 to 31
support clock rates up to 10 MHz. In
the special case where no more than 3
high-speed links are used, the
maximum aggregate link clock-rate is
156 MHz.
• Links configured for channelized
T1/J1/E1 or unchannelized operation
support the gapped-clock method for
determining time-slots, which is
backwards compatible with the
FREEDM-8 and FREEDM-32 devices.
• For each channel, the HDLC receiver
supports programmable flag-sequence
detection, bit de-stuffing and
frame-check sequence validation. The
receiver supports the validation of both
CRC-CCITT and CRC-32 frame-check
sequences.
• For each channel, the HDLC
transmitter supports programmable
flag-sequence generation, bit stuffing
and frame-check sequence
generation. The transmitter supports
the generation of both CRC-CCITT
and CRC-32 frame-check sequences.
The transmitter also aborts packets
under the direction of the host or
automatically when the channel
underflows.
• Provides 32 kbytes of on-chip memory
for partial packet buffering in both the
transmit and receive directions. You
can configure this memory to support a
variety of different channel
configurations: from a single channel
with 32 kbytes of buffering, to 256
channels, each with a minimum of 48
bytes of buffering.
• Provides a standard five signal
P1149.1 JTAG test-port for boundary
scan board-test purposes.
RSTB
SYSCLK
PMCTEST
BLOCK DIAGRAM
RBD
RBCLK
RD[31:0]
RCLK[31:0]
RFPB[3:0]
RMVCK[3:0]
RMV8DC
RMV8FPC
RFP8B
AD[31:0]
C/BEB[3:0]
PAR
Receive
Channel
Assigner
(RCAS256)
Receive HDLC
Processor/Partial
Packet Buffer
(RHDL256)
Receive
DMA
Controller
(RMAC256)
PCI
Controller
(GPIC256)
FRAMEB
TRDYB
IRDYB
STOPB
DEVSELB
IDSEL
LOCKB
REQB
GNTB
PERRB
SERRB
PCIINTB
PCICLK
PCICLKO
M66EN
Performance
Monitor (PMON)
TD[31:0]
TCLK[31:0]
TFPB[3:0]
TMVCK[3:0]
TMV8DC
TMV8FPC
TFP8B
Transmit
DMA
Controller
(TMAC256)
Transmit
Channel
Assigner
(TCAS256)
Transmit HDLC
Processor/ Partial
Packet Buffer
(THDL256)
JTAG Port
TBCLK
TBD
TDO
TDI
TMS
TCK
TRSTB
PMC-2011578 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2001
PMC [ PMC-SIERRA, INC ]
