RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
or E1 rates and may range up to a maximum clock rate of 51.84 MHz for
TCLK[2:0] and 10 MHz for TCLK[31:3]. The link clock is only active during bit
times containing data to be transmitted and inactive during bits that are to be
ignored by the downstream devices, such as framing and overhead bits. For the
case of two unchannelised links, the maximum link rate is 51.84 MHz. For the
case of more numerous unchannelised links or a mixture of channelised,
unchannelised and H-MVIP links, the total instantaneous link rate over all the
links is limited to 64 MHz.
9.9.1 Line Interface Translator (LIT)
The LIT block translates the information between the 32 physical links and the
Line Interface block. The LIT block performs three functions: data translation,
clock translation and frame pulse generation.
When link 4m (0?m?7) is configured for operation in 8.192 Mbps H-MVIP mode,
the LIT block translates the data arriving from the Line Interface block on links
4m, 4m+1, 4m+2 and 4m+3 onto the 128 time-slot link 4m. The LIT block
translates data arriving from the Line Interface block on link 4m, 4m+1, 4m+2
and 4m+3 onto time-slots 0 through 31, 32 through 63, 64 through 95 and 96
through 127 respectively. When link 4m is configured for operation in 8.192
Mbps H-MVIP mode, outputs TD[4m+3:4m+1] are driven with constant ones.
However, links 4m+1, 4m+2 and 4m+3 must be programmed in the TCAS672
Link Configuration register for 8.192 Mbps H-MVIP operation. When links are
configured for operation in 2.048 Mbps H-MVIP mode, channelised T1/J1/E1
mode or unchannelised mode, the LIT block does not perform any translation on
the link data.
When a link is configured for operation in H-MVIP mode, the LIT block divides
the appropriate clock (TMVCK[n] for 2.048 Mbps H-MVIP and TMV8DC for 8.192
Mbps H-MVIP) by two and provides this divided down clock to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the LIT block does not perform any translation on the link
clock.
When a link is configured for operation in H-MVIP mode, the LIT block samples
the appropriate frame pulse (TFPB[n] for 2.048 Mbps H-MVIP and TFP8B for
8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the gapped clock is passed to the LIT block unmodified.
9.9.2 Line Interface
There are 32 identical line interface blocks in the TCAS672. Each line interface
block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
82
PMC [ PMC-SIERRA, INC ]
