RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Pin Name Type
Pin
Function
No.
PERRB
I/O
T3
The active low parity error signal (PERRB)
indicates a parity error over the AD[31:0] and
C/BEB[3:0] buses. Parity error is signalled
when even parity calculations do not match the
PAR signal. PERRB is set low at the cycle
immediately following an offending PAR cycle.
PERRB is set high when no parity error is
detected.
PERRB is enabled by setting the PERREN bit in
the Control/Status register in the PCI
Configuration registers space. Regardless of
the setting of PERREN, parity errors are always
reported by the PERR bit in the Control/Status
register in the PCI Configuration registers
space.
PERRB is updated on the rising edge of
PCICLK.
SERRB
OD
T2
The active low system error signal (SERRB)
indicates an address parity error. Address parity
errors are detected when the even parity
calculations during the address phase do not
match the PAR signal. When the FREEDM-
32P672 detects a system error, SERRB is set
low for one PCICLK period.
Output
SERRB is enabled by setting the SERREN bit in
the Control/Status register in the PCI
Configuration registers space. Regardless of
the setting of SERREN, parity errors are always
reported by the SERR bit in the Control/Status
register in the PCI Configuration registers
space.
SERRB is an open drain output and is updated
on the rising edge of PCICLK.
M66EN
Input
AC2
The active high 66 MHz mode enable signal
(M66EN) reflects the speed of operation of the
PCI bus. M66EN should be set high for 66 MHz
operation on the PCI bus. M66EN should be
set low for 33 MHz operation on the PCI bus.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
PMC [ PMC-SIERRA, INC ]
