RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Pin Name Type
Pin
Function
No.
AD[0]
I/O
AC1
AB1
AA3
AA1
AA2
Y3
The PCI address and data bus (AD[31:0])
carries the PCI bus multiplexed address and
data. During the first clock cycle of a
AD[1]
AD[2]
AD[3]
transaction, AD[31:0] contains a physical byte
address. During subsequent clock cycles of a
transaction, AD[31:0] contains data.
AD[4]
AD[5]
AD[6]
W4
Y1
A transaction is defined as an address phase
followed by one or more data phases. When
Little-Endian byte formatting is selected,
AD[7]
AD[8]
W3
W1
V3
AD[9]
AD[31:24] contain the most significant byte of a
DWORD while AD[7:0] contain the least
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
V1
significant byte. When Big-Endian byte
V2
formatting is selected. AD[7:0] contain the most
significant byte of a DWORD while AD[31:24]
contain the least significant byte. When the
FREEDM-32P672 is the initiator, AD[31:0] is an
output bus during the first (address) phase of a
transaction. For write transactions, AD[31:0]
remains an output bus for the data phases of
the transaction. For read transactions, AD[31:0]
is an input bus during the data phases.
U1
U4
U2
N4
N1
N3
N2
M2
M3
L3
When the FREEDM-32P672 is the target,
AD[31:0] is an input bus during the first
(address) phase of a transaction. For write
transactions, AD[31:0] remains an input bus
during the data phases of the transaction. For
read transactions, AD[31:0] is an output bus
during the data phases.
L2
K3
K2
K1
J3
J2
J4
When the FREEDM-32P672 is not involved in
J1
the current transaction, AD[31:0] is tristated.
H3
As an output bus, AD[31:0] is updated on the
rising edge of PCICLK. As an input bus,
AD[31:0] is sampled on the rising edge of
PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
24
PMC [ PMC-SIERRA, INC ]
