RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
C1[15:0]:
The C1[15:0] bits reports the number of selected events that have been
detected since the last time this register was polled. This register is polled by
writing to the FREEDM-32P672 Master Clock / BERT Activity Monitor and
Accumulation Trigger register. The write access transfers the internally
accumulated error count to the configurable count #1 register and
simultaneously resets the internal counter to begin a new cycle of event
accumulation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
249
PMC [ PMC-SIERRA, INC ]
