RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x31C TMAC Descriptor Reference Free Queue Write
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDRFQW[15]
TDRFQW[14]
TDRFQW[13]
TDRFQW[12]
TDRFQW[11]
TDRFQW[10]
TDRFQW[9]
TDRFQW[8]
TDRFQW[7]
TDRFQW[6]
TDRFQW[5]
TDRFQW[4]
TDRFQW[3]
TDRFQW[2]
TDRFQW[1]
TDRFQW[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the Transmit Descriptor Reference Free Queue write
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
196
PMC [ PMC-SIERRA, INC ]
