RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x280 : RMAC Control
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXH
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
RPQ_SFN[1]
RPQ_SFN[0]
RPQ_LFN[1]
RPQ_LFN[0]
RPQ_RDYN[2]
RPQ_RDYN[1]
RPQ_RDYN[0]
RAWMAX[1]
RAWMAX[0]
SCACHE
0
0
0
0
0
0
0
0
1
1
1
1
0
LCACHE
ENABLE
This register configures the RMAC672 block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
ENABLE:
The ENABLE bit determines whether or not the RMAC672 accepts data from
the RHDL672 block and sends it to host memory. When set to 1, these tasks
are enabled. When set to 0, they are disabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
149
PMC [ PMC-SIERRA, INC ]
