RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Figure 50 – BERT Output Timing
RBCLK
tPRBD
RBD
Table 37 – PCI Interface (Figure 51)
Symbol
Description
Min
Max
Units
PCICLK Frequency (See Note 1)
PCICLK Duty Cycle
25
40
4
66
60
MHz
%
ns
tS
All PCI Input and Bi-directional Set-
PCI
up time to PCICLK
tH
All PCI Input and Bi-directional Hold 0.5
time to PCICLK
ns
PCI
t
t
PCICLK to all PCI Outputs Valid
2
8.5
14
ns
ns
P
PCI
PCI Output active from PCICLK to
Tristate
Z
PCI
t
All PCI Outputs Tristate from
2
ns
ZN
PCI
PCICLK to active
Notes on PCI Timing:
1. PCICLK cannot change frequency without resetting the FREEDM-32P672
device.
2. The phrase “all PCI Outputs” in the above table excludes PCIINTB and
PCICLKO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
315
PMC [ PMC-SIERRA, INC ]
