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PM7380 参数 Datasheet PDF下载

PM7380图片预览
型号: PM7380
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
14  
FUNCTIONAL TIMING  
14.1 Receive H-MVIP Link Timing  
The timing relationship of the receive data clock (RMV8DC), frame pulse clock  
(RMV8FPC), data (RD[n]) and frame pulse (RFP8B[n]) signals of a link  
configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown  
in Figure 23. The falling edges of each RMV8FPC are aligned to a falling edge  
of the corresponding RMV8DC for 8.192 Mbps H-MVIP operation. The  
FREEDM-32P672 samples RFP8B low on the falling edge of RMV8FPC and  
references this point as the start of the next frame. The FREEDM-32P672  
samples the data provided on RD[n] at the ¾ point of the data bit using the rising  
edge of RMV8DC as indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 23.  
B1 is the most significant bit and B8 is the least significant bit of each octet.  
Time-slots can be ignored by setting the PROV bit in the corresponding word of  
the receive channel provision RAM in the RCAS672 block to low.  
Figure 23 – Receive 8.192 Mbps H-MVIP Link Timing  
RMV8DC  
(16 MHz)  
RMV8FPC  
(4 MHz)  
RFP8B  
RD[n]  
B8  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B1  
TS 1  
TS 127  
TS 0  
The timing relationship of the receive data clock (RMVCK[n]), data (RD[m],  
where 8n?m?8n+7) and frame pulse (RFPB[n]) signals of a link configured for  
2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 24.  
The FREEDM-32P672 samples RFPB[n] low on the falling edge of the  
corresponding RMVCK[n] and references this point as the start of the next  
frame. The FREEDM-32P672 samples the data provided on RD[m] at the ¾  
point of the data bit using the rising edge of the corresponding RMVCK[n] as  
indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 24. B1 is the most  
significant bit and B8 is the least significant bit of each octet. Time-slots can be  
ignored by setting the PROV bit in the corresponding word of the receive channel  
provision RAM in the RCAS672 block to low.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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