RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x40C : TCAS Idle Time-slot Fill Data
Bit
Type
Function
Default
Bit 31
Unused
XXXXXXH
to
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FDATA[7]
FDATA[6]
FDATA[5]
FDATA[4]
FDATA[3]
FDATA[2]
FDATA[1]
FDATA[0]
1
1
1
1
1
1
1
1
This register contains the data to be written to disabled time-slots of a
channelised link.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
FDATA[7:0]:
The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low)
time-slots of channelised links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
235
PMC [ PMC-SIERRA, INC ]
