RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
BURSTEN:
The burst length enable bit (BURSTEN) controls the use of BURST[3:0] in
determining the amount of data requested in a single DMA transaction for
channels whose channel transfer size is set to one block (XFER[3:0] =
'b0000). BURSTEN has no effect on channels configured with other transfer
sizes. When BURSTEN is set high, the maximum size of DMA transfer is
limited by BURST[3:0]. The transmit HDLC processor may combine several
channel transfer size amounts into a single transaction. When BURSTEN is
set low, the amount of data in a DMA transfer is limited to one block.
TSTD:
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data
transferred from the PCI host. When TSTD is set low, the least significant bit
of the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24]) is the first
HDLC bit transmitted and the most significant bit of each byte (AD[7], AD[15],
AD[23] and AD[31]) is the last HDLC bit transmitted (datacom standard).
When TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC
bit transmitted and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit
transmitted (telecom standard).
BIT8:
The least significant stuff control bit (BIT8) carries the value placed in the
least significant bit of each octet when the HDLC processor is configured
(7BIT set high) to stuff the least significant bit of each octet in the
corresponding transmit link (TD[n]). When BIT8 is set high, the least
significant bit (last bit of each octet transmitted) is forced high. When BIT8 is
set low, the least significant bit is forced low. BIT8 is ignored when 7BIT is set
low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
