RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
9.2
Receive Channel Assigner
The Receive Channel Assigner block (RCAS) processes up to 8 serial links. Each link is
independent and has its own associated clock. For each link, the RCAS performs a serial to
parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for
delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL) at SYSCLK rate. In
the event where multiple streams have accumulated a byte of data, multiplexing is performed on a
fixed priority basis with link #0 having the highest priority and link #7 the lowest.
Links containing a T1 or an E1 stream may be channelised. Data at each time-slot may be
independently assigned to a different channel. The RCAS performs a table lookup to associate
the link and time-slot identity with a channel. T1 and E1 framing bits/bytes are identified by
observing the gap in the link clock which is squelched during the framing bits/bytes. For
unchannelised links, clock rates are limited to 52 MHz on link #0 to #2 and limited to 10 MHz for
the remaining links. All data on each link belongs to one channel. For the case of two
unchannelised links, the maximum link rate is 52 MHz for SYSCLK at 33 MHz. For the case of
more numerous unchannelised links or a mixture of channelise with unchannelised links, the total
instantaneous link rate over all the links is limited to 64 MHz. The RCAS performs a table lookup
using only the link number to determine the associated channel, as time-slots are non-existent in
unchannelised links.
The RCAS provides diagnostic loopback that is selectable on a per channel basis. When a
channel is in diagnostic loopback, stream data on the received links originally destined for that
channel is ignored. Transmit data of that channel is substituted in its place.
9.2.1 Line Interface
There are 8 identical line interface blocks in the RCAS. Each line interface contains a bit counter,
an 8-bit shift register and a holding register, that, together, perform serial to parallel conversion.
Whenever the holding register is updated, a request for service is sent to the priority encoder
block. When acknowledged by the priority encoder, the line interface would respond with the data
residing in the holding register.
To support channelised links, each line interface block contains a time-slot counter and a clock
activity monitor. The time-slot counter is incremented each time the holding register is updated.
The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is
cleared by a rising edge of the receive clock (RCLK[n]). A framing bit (T1) or framing byte (E1) is
detected when the counter reaches a programmable threshold. In which case, the bit and time-
slot counters are initialised to indicate that the next bit is the most significant bit of the first time-
slot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset.
9.2.2 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises them to the
SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to
lowest priority is assigned from the line interface attached to RD[0] to that attached to RD[7].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
