RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x50C : PMON Configurable Count #1
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
C1[15]
C1[14]
C1[13]
C1[12]
C1[11]
C1[10]
C1[9]
C1[8]
C1[7]
C1[6]
C1[5]
C1[4]
C1[3]
C1[2]
C1[1]
C1[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register reports the number events, selected by the FREEDM-8 Master Performance Monitor
Control register, that occurred in the previous accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
C1[15:0]:
The C1[15:0] bits reports the number of selected events that have been detected since the
last time this register was polled. This register is polled by writing to the FREEDM-8 Master
Clock / BERT Activity Monitor and Accumulation Trigger register. The write access transfers
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
212
PMC [ PMC-SIERRA, INC ]
