RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
syndrome for the preceding cell. A non-zero remainder shall result in a
maskable interrupt and, if enabled by the CNTCELLERR bit, a cell error count
increment. If CELLCRC is logic 0, the contents of the second User Prepend
byte are not examined.
CNTCELLERR:
The CNTCELLERR bit allows the redefinition of the Receive High-Speed
Serial HCS Error Count register to include the number of cell CRC-8 errors.
If CNTCELLERR and CELLCRC are logic 1, each non-zero remainder for the
CRC-8 protecting the entire cell or non-zero remainder HCS results in an
increment. (Simultaneous cell CRC-8 and HCS errors result in a single
increment.) If either CNTCELLERR or CELLCRC is logic 0, the count
represents the number of HCS errors.
DDSCR and HDSCR:
The Disable Descramble (DDSCR) and Header Descramble enable (HDSCR)
bits control the descrambling of the cell by the x43 + 1 self-synchronous
descrambler. When DDSCR is a logic one, cell header and payload
descrambling is disabled. When DDSCR is a logic zero, payload
descrambling is enabled and cell header descrambling is determined by
HDSCR. HDSCR enables descrambling of the System Prepend, User
Prepend, User Header, and HCS byte collectively. The operation of the
DDSCR and HDSCR bits is summarized below:
DDSCR HDSCR Operation
1
0
0
X
0
1
Cell payload and header descrambling is
disabled. THIS CONFIGURATION SHOULD
ONLY BE USED FOR DIAGNOSTIC
PURPOSES.
Cell payload is descrambled. Cell header is
left unscrambled. THIS CONFIGURATION
SHOULD ONLY BE USED FOR
DIAGNOSTIC PURPOSES.
Cell payload and header are both
descrambled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
87
PMC [ PMC-SIERRA, INC ]
