RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Register 0x01D: Microprocessor Cell Buffer Data
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MCDAT[7]
MCDAT[6]
MCDAT[5]
MCDAT[4]
MCDAT[3]
MCDAT[2]
MCDAT[1]
MCDAT[0]
X
X
X
X
X
X
X
X
MCDAT[7:0]:
The MCDAT[7:0] is used to write to the selected Microprocessor Insert FIFO
or read from the selected Microprocessor Extract FIFO by the
microprocessor.
When inserting cells, the Microprocessor Insert FIFO Ready register may be
polled to determine which FIFO is ready to receive a cell. Alternately, an
interrupt may be generated by setting the Microprocessor Insert FIFO
Interrupt Enable Register bit accordingly. Selection of the Microprocessor
Insert FIFO is done by writing the INSFSEL[2:0] bits of the Microprocessor
Insert FIFO Control Register. A cell is transferred to a Microprocessor Insert
FIFO by performing successive write accesses to the Microprocessor Cell
Data register. The rising edge of WRB for two successive write accesses to
this register must separated by at least three REFCLK periods.
When extracting cells, the Microprocessor Extract FIFO Ready register may
be polled to determine which FIFO has a cell available to be read.
Alternately, an interrupt may be generated by setting the Microprocessor
Extract FIFO Interrupt Enable Register bit accordingly. Selection of the
Microprocessor Extract FIFO is done by writing the EXTFSEL[2:0] bits of the
Extract FIFO Control Register. A cell is transferred from an Extract FIFO by
performing successive read accesses to the Microprocessor Cell Data
register. The falling edge of RDB for two successive read accesses to this
register must separated by at least three REFCLK periods.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
85
PMC [ PMC-SIERRA, INC ]
