RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
cell (i.e. a cell is transferred from a full FIFO) or upon the completion of a cell
write if at least one more cell can be written. The ready status of a specific
FIFO is indicated by a logic 1 at the corresponding bit of the Microprocessor
Insert FIFO Ready register. The INSRDYI bit is reset immediately after a
read to this register.
INSOVRI:
The INSOVRI bit indicates the status of the write access to a Microprocessor
Insert FIFO. This bit is set to logic 1 when a write access has being
attempted to a full Microprocessor Insert FIFO and the data has been
discarded. This bit is reset immediately after a read to this register.
EXTRDYI:
The EXTRDYI bit provides a status of the Microprocessor Extract FIFOs
Ready Interrupt. This bit is set to logic 1 when one of the Microprocessor
Extract FIFOs becomes ready for a cell read (i.e. upon reception of the only
cell in the FIFO) or upon the completion of a cell read if there is at least one
more cell to be read from the FIFO. Ready status of a specific FIFO is
indicated by a logic 1 at the corresponding bit of the Microprocessor Extract
FIFO Ready register. The EXTRDYI bit is reset immediately after a read to
this register.
EXTCRCERRI:
The EXTCRCERRI bit indicates the CRC-32 status of a cell read from an
Extract FIFO. When the EXTCRCCHK bit is set to logic 1, the EXTCRCERRI
bit is updated when the last byte of a cell is read by the microprocessor. It is
set to logic 1 if the value of the Extract CRC Accumulator register differs from
the expected CRC-32 remainder polynomial. Otherwise, it is set to logic 0.
This bit is also reset immediately after a read to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PMC [ PMC-SIERRA, INC ]
